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Fixes Issue 2584: delays LRCK to falling edge of BCK in I2S input #2592
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Fixing Issue 2584 bug: in input mode, LRCK needs to change on falling edge of BCK
Fixes Issue 2584: I2S input, LRCK should change on falling edge of BCK
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Does the comment on line 153 of the .pio file need updating? |
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Not to my mind. My comment was that the change was "only for input mode" because the output mode already has the correct timing. |
earlephilhower
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Awesome, thank you very much!
Could you apply the same fix to pio_i2s_in_swap for completeness? It's the same program with the BCLK/LRCLK pins reversed.
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I'd be happy to make that fix, but.... can someone confirm that swapClocks is working for inputs? It works fine for I2S outputs, but appears to have no effect for inputs. The bits look properly swapped in the PIO input code, so either it's in the C code or I'm doing something silly. |
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Not sure I understand the question, sorry. The "swap clocks" versions here refer to just changing the order of the BCLK/WCLK in the PIO sidesets. So |
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You're right; it's a trivial change. The problem came when I tried to test it and discovered that, for whatever reason, the clock-swapped PIO code wasn't being run. Just to make sure, I then ran swapClocks() when setting up the output I2S, which did swap the clocks. So either I'm doing something wrong or there's a bug in the library C code. If this isn't an open issue, I can dive into the library code and see why it's not calling the right PIO routine. |
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Yes, please do the change. We can debug the swapclocks bit elsewhere. Thx! |
Issue 2584, extended LRCK for swapped clock input version
Delayed LRCK for swapped I2S in
earlephilhower
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Thanks again! With HW-related bugs like this it really helps to have a user submit a tested solution!
2 changes in pio_i2s.pio (stamped 2584) to delay the transitions on LRCK until the falling edge of BCK. Only for input mode. TI ADCs usually prefer that timing.